1. Field of the Invention
The present invention is generally directed to the field of semiconductor processing, and, more particularly, to a method of forming source/drain regions in a semiconductor device.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase overall performance and operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase device performance and the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
With this continual drive to increase transistor performance, all aspects of device operation must be examined for purposes of enhancing device performance. For example, leakage currents that may occur whenever a semiconductor device, e.g., a transistor, is xe2x80x9conxe2x80x9d or xe2x80x9coff,xe2x80x9d must be reduced. One factor that tends to increase these leakage currents is having source/drain junctions of an insufficient depth. Typically, a contact comprised of a metal silicide, e.g., cobalt silicide, is formed above a source/drain region to facilitate the electrical connection of a conductive line to the source/drain region, i.e., the metal silicide region is used to reduce the contact resistance. If the depth of the junction, which is generally understood to be at a point at which the concentration of N-dopant atoms and P-type dopant atoms are approximately equal, is not deep enough, then there may be leakage currents when the device is either xe2x80x9conxe2x80x9d or xe2x80x9coff.xe2x80x9d Thus, in general, it is desirable to form source/drain regions in which the junction depth is deeper rather than shallower.
In general, source/drain regions may be formed by a variety of techniques. For example, source/drain regions may be formed by performing multiple ion implantation processes in which various dopant atoms are implanted into a semiconducting substrate. An initial ion implantation process may be performed to form relatively shallow, extension implants in the substrate. Thereafter, after sidewall spacers are formed adjacent the gate stack, a traditional source/drain implant may be performed at a relatively heavy dopant concentration, but much deeper than the initial extension implants. Next, another implant process, typically referred to as a co-implant process, may be performed in an effort to achieve greater junction depths. However, the lateral diffusion of these deeper junctions prevent the depth of the junction from going deeper than approximately 1500 xc3x85 using traditional process flows.
Another problem associated with source/drain regions is capacitance. In general, it is desirable to reduce the capacitance caused by the source/drain regions to enhance device performance. This capacitance must be charged and discharged every operating cycle in which the transistor the transistor is turned xe2x80x9conxe2x80x9d or xe2x80x9coff.xe2x80x9d This results in RC time delays with respect to signal propagation throughout the device, as well as an increase in the power consumed by the device during operation. In general, it would be desirable to have source/drain regions with a more gradual dopant concentration profile to reduce the capacitance of the source/drain regions.
The present invention is directed to a method that solves or at least reduces some or all of the aforementioned problems.
The present invention is directed to a method of forming source/drain regions in a semiconductor device. In one illustrative embodiment, the method comprises forming a gate stack above a semiconducting substrate, forming a recess in the substrate adjacent the gate stack, the recess having a bottom surface, and performing a first ion implantation process into the bottom surface of the recess to form a first doped region. The method further comprises forming a layer of epitaxial silicon in said recess, performing a second ion implantation process to form a second doped region in at least a portion of the epitaxial silicon layer in the recess, and annealing the first and second doped regions.